Memory cells typically comprise a storage element for storing an electrical charge which represents information to be stored, and an access transistor which is connected to the storage element. In particular, in a Dynamic Random Access Memory (DRAM), the storage element is implemented as a storage capacitor. The access transistor comprises first and second source/drain regions, a channel connecting the first and the second source/drain regions, and a gate electrode controlling an electrical current flow between the first and second source/drain regions. The transistor usually is at least partially formed in the semiconductor substrate. The gate electrode forms part of a wordline and is electrically isolated from the channel by a gate dielectric. By addressing the access transistor via the corresponding wordline, the information stored in the storage capacitor is read out. In particular, the information is read out to a corresponding bitline via a bitline contact.
In the currently used DRAM memory cells, the storage capacitor may be implemented as a trench capacitor in which the two capacitor electrodes are disposed in a trench which extends into the substrate in a direction perpendicular to the substrate surface. According to another implementation of the DRAM memory cell, the electrical charge is stored in a stacked capacitor which is formed above the surface of the substrate.
Generally, a DRAM memory cell array is desired that includes a higher packaging density and which may be produced by a simple, robust process having a low complexity and a high yield. At the same time, it is desirable to obtain optimum characteristics of the access transistor.
Accordingly, an improved transistor as well as an improved method of manufacturing such a transistor are needed. In addition, an improved memory cell array as well as an improved method of forming such a memory cell array are desired.